■ 基本信息
姓 名： 刘大江
性 别： 男
职 称： 副教授(硕导)
职 务：
电 话：
办公地点： 主教1815
E-mail：liudj@cqu.edu.cn
研究方向： 可重构计算体系结构、高能效编译工具、高层次综合、图计算架构
招生信息： 招收硕士研究生，欢迎计算机科学与技术、电子科学与技术、自动化等专业考生报考。
■ 个人简介：
刘大江，博士，重庆大学计算机学院副教授、硕士生导师；2009年本科毕业于电子科技大学微电子技术专业；同年9月进入清华大学微纳电子系直接攻读博士学位，2015年获得工学博士学位；同年8月进入清华大学计算机系进行博士后研究，2017年出站；同年9月进入重庆大学计算机学院工作至今，现为重庆大学计算机学院副教授，于2018年在澳大利亚昆士兰大学和悉尼科技大学进行访问交流。研究领域包括粗粒度可重构计算架构及编译、图计算架构和神经网络编译等；曾主持和参与了国家自然科学基金和CCF-腾讯犀牛鸟基金等多个项目；在DAC、ICCAD、DATE、TCAD、TVLSI等重要国际会议和期刊发表二十余篇论文；现为IEEE和中国计算机协会会员；曾获教育部科技成果完成者证书。
■ 5篇代表性论文（*通信作者）：
[DAC'23] D. Liu*, D. Mou, R. Zhu, J. Shang, J. Zhong, and S. Yin, "DARIC: A Data Reuse-Friendly CGRA for Parallel Data Access via Elastic FIFOs", in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1-6.
[DAC'23] L. Huang, and D. Liu*, "Optimizing Data Reuse for CGRA Mapping Using Polyhedral-based Loop Transformations", in 2023 60th ACM/IEEE Design Automation Conference (DAC), 2023, pp. 1-6.
[ICCAD'22] Y. Zhuang, Z. Zhang, and D. Liu*, "Towards High-Quality CGRA Mapping with Graph Neural Networks and Reinforcement Learning", in 2022 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2022, pp. 1-9.
[ICCAD'22] D. Liu*, T. Liu, X. Mo, J. Shang, J. Zhong, and S. Yin, "Polyhedral-based Pipelining of Imperfectly-Nested Loop for CGRAs", in 2021 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2021, pp. 1-9.
[TCAD'19] D. Liu*, S. Yin, G. Luo, J. Shang, L. Liu, S. Wei, Y. Feng, and S. Zhou, "Data-Flow Graph Mapping Optimization for CGRA with Deep Reinforcement Learning", IEEE Trans. on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, vol. 38, no. 12, pp. 2271-2283, 2019.
■ 其他代表性论文（*通信作者）：
[ASP-DAC'23] B. Liu, and D. Liu*, "Towards High-Bandwidth-Utilization SpMV on FPGAs via Partial Vector Duplication", in 2023 IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), 2023, pp.33-38.
[SYSTOR'23] L. Lei, D. Pan, D. Liu*, P. Ouyang, and X. Du, Optimizing Memory Allocation for Multi-Subgraph Mapping on Spatial Accelerators, in 2023ACM International Conference on Systems and Storage (SYSTOR), 2023, pp. 105-110.
[DATE'22] R. Zhu, B. Wang, and D. Liu*, "RF-CGRA: A Routing-Friendly CGRA with Hierarchical Register Chains", in 2022 Design, Automation and Test in Europe Conference (DATE), 2022, pp. 262-267.
[DATE'22] B. Wang, R. Zhu, J. Shang, and D. Liu*, "Towards Energy-Efficient CGRAs via Stochastic Computing", in 2022 Design, Automation and Test in Europe Conference (DATE), 2022, pp. 202-207.
[ISCAS'17] S. Yin, D. Liu, L. Sun, L. Liu, and S. Wei, "DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach", in IEEE International Symposium on Circuits and Systems (ISCAS), 2017, pp. 1-4.
[TPDS'17] S. Yin, X. Yao, T. Lu, D. Liu, L. Liu, and S. Wei, "Conflict-Free Loop Mapping for Coarse-Grained Reconfigurable Architecture with Multi-Bank Memory", IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 28, no. 9, pp. 2471–2485, 2017.
[TVLSI'16] S. Yin, D. Liu, Y. Peng, L. Liu, and S. Wei, "Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 24, no. 2, pp. 507-520, 2016.
[TVLSI'16] S. Yin, X. Yao, D. Liu, L. Liu, and S. Wei, "Memory-aware loop mapping on coarse-grained reconfigurable architectures", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol 24, no. 5, pp. 1895-1908, 2016.
[TCAD'16] S. Yin, J. Gu, D. Liu, L. Liu, and S. Wei, "Joint modulo scheduling and Vdd assignment for loop mapping on dual-Vdd CGRAs", IEEE Trans. on Computer-Aided Design (TCAD) of Integrated Circuits and Systems, vol. 35, no. 9, pp. 1475–1488, 2016.
[TVLSI'15] D. Liu, S. Yin, Y. Peng, L. Liu, and S. Wei, "Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures", IEEE Transactions on Very Large Scale Integration (TVLSI) Systems , vol. 23, no. 11, pp. 2581-2594, 2015.
[DATE'15] S. Yin, D. Liu, L. Liu, S. Wei, and Y. Guo, "Joint affine transformation and loop pipelining for mapping nested loop on CGRAs", in 2015 Design, Automation and Test in Europe Conference (DATE), 2015, pp. 1-6.
[IEICE'15] D. Liu, S. Yin, L. Liu, and S. Wei, "Mapping multi-level loop nests onto CGRAs using polyhedral optimizations", IEICE TRANSACTIONS on Fundamentals, 98-A(7), pp. 1419-1430, 2015.
[DAC'13] D. Liu, S. Yin, L. Liu, and S. Wei, "Polyhedral model based mapping optimization of loop nests for CGRAs", in 2023 50th ACM/EDAC/IEEE Design Automation Conference (DAC), 2013, pp. 1-8.
[ISCAS'13] D. Liu, S. Yin, L. Liu, and S. Wei, "Affine transformations for communication and reconfiguration optimization of loops on CGRAs", in 2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, pp. 2541-2544.
[IEICE'12] D. Liu, S. Yin, C. Yin, L. Liu, and S. Wei, "Mapping optimization of affine loop nests for reconfigurable computing architecture", IEICE transactions on electronics, E95-D(12), pp. 1284–1290, 2012.
■ 科研项目
1. 国家自然科学基金面上项目，62274019，基于跨层优化的高能效动态可重构计算芯片关键技术研究，2023-2026，在研，主持
2. 国家自然科学基金青年项目，61804017，软件定义硬件中数据密集型应用的高性能映射技术研究，2019 - 2021，已结题，主持
3. 清微智能技术合作项目，可重构处理器数据流图空间映射优化，2021-2022，已结题，主持
4. CCF-腾讯犀牛鸟基金，面向数据密集型应用的可重构处理器高性能映射技术研究，2018-2019，已结题，主持
■ 教学课程
1. 2020-2021，《高级硬件设计》（数字电路高层次综合），本科专业课，3 学分
2. 2020-2021，《计算机系统结构》，本科专业课，2.5 学分
3. 2021年春季，《大数据智能与深度学习》，本科专业课，3 学分
4. 2019年秋季，《数字逻辑》，本科专业课，3.5 学分
5. 2018-2021，《学术规范与论文写作指导》，研究生专业课，1 学分
